One or more embodiments relate generally to semiconductor packaging, and more particularly to a semiconductor device having two conductive pads and a method of manufacturing the same.
When packaging a semiconductor chip after circuitry has been formed thereon, interconnections between the circuitry on the chip and the input/output connecting pins on a package substrate may be implemented by Flip-Chip packaging technology. A Flip-Chip assembly includes a direct electric connection of a face down (that is, “flipped”) semiconductor chip onto a package substrate, such as a ceramic substrate, a circuit board, or a carrier using conductive bumps disposed on the semiconductor chip. Flip-Chip technology is quickly replacing older wire bonding technology that uses face up semiconductor chips with the wire connected to each pad on the semiconductor chips.
To package a semiconductor chip using Flip-Chip packaging technology, the semiconductor chip is flipped and positioned on a package substrate. Conductive bumps are reflowed to form electric connections between the semiconductor chip and package substrate and provide limited mechanical mounting for the semiconductor chip and the package substrate. During the reflow process, flux is used to facilitate the joining of the conductive bumps, bond pads on the semiconductor chip, and pads on the packaging substrate. Then, excessive flux residues are removed, and an underfill adhesive, such as epoxy, is used to fill spaces between the semiconductor chip and the package substrate in order to provide even better mechanical interconnection between the semiconductor chip and the package substrate. This increases the reliability and fatigue resistance of the package interconnections and minimizes uneven stress distribution caused by thermally induced strains due to the differences in coefficients of thermal expansion (CTE) between the semiconductor chip and package substrate.
As mentioned, the Flip-Chip packaging technology involves flipping a semiconductor chip onto a package substrate and heating the flipped semiconductor chip. These operations impose a great amount of stress and strain to the semiconductor chip. With increasing utilization of mechanically weaker materials, such as low dielectric constant (low-k) materials, semiconductor chips are more vulnerable to stress and strain than those where non-low-k materials are used instead. Further, as sizes of semiconductor chips increase, the stress and strain associated with the packaging process also increases.